Analog design,faster. Smarter.
At a fraction of the cost.

Vedic Analog is reimagining how analog chips are designed — bringing together cutting-edge AI and deep domain expertise to serve the global semiconductor industry.

VA-AGENT CHAT Design 2-stage amp: gain=40dB BW=2MHz CL=10pF VDD=1.8V U ▶ Sizing M1/M2 W/L=10 ▶ Sizing M6 W/L=20 ✓ Gain=40dB ready AI Increase gain to 60 dB Need stronger output Keep BW > 1.5 MHz U ▶ 2-stage = 40dB max ▶ Adding Stage 3... ▶ M8/M9 inserted ✦ ✓ Gain = 60.4 dB AI Set phase margin 70° Tune Cc for stability U ▶ Cc: 2.1→3.4pF ✓ ▶ Layout updated ✓ PM=70.2° CMRR=86dB AI ✓ FIRST-PASS SUCCESS 3-stage · 4h 28m Increase gain to 60dB... Set phase margin 70°... Minimize die area... Add cascode for CMRR... ↑ VA-AGENT · AUTONOMOUS ANALOG DESIGN ◉ CMOS SCHEMATIC 2-STAGE 3-STAGE! VDD M3 M4 M1 Vin+ M2 Vin- A M5 Vb M7 Vb2 M6 V1 NEW ✦ M9 M8 Vout Cc ▶ agent optimizing transistor topology... ◉ IC LAYOUT N-WELL VDD MP1 MP2 MN1 MN2 M7 M6 M9 NEW M8 NEW OUT Itail POLY DIFF MET1 MET2 ▶ auto-routing layout... Area: 186μm² ◉ SIMULATION 40dB 60dB ✦ PM=70.2° CH1 2.40MHz 2.0Vpp CH2 Gain 40.1dB φ90° CH2 Gain 60.4dB φ90° AC Gain THD 0.02% Input Output Gain Monte Carlo n=1000 90% ◉ VERIFICATION ALL PASS ✓ DRC Clean PASS ✓ LVS Verified PASS ✓ DC Gain 40.1 dB DC Gain 60.4 dB ✦ PASS ✓ Phase Margin 70.2° PASS ✓ CMRR 86 dB PASS ✓ THD 0.02% PASS ✓ Power 3.1 mW PASS ✓ Die Area 186 μm² OPTIMAL ✓ GBW 10.2 MHz PASS ✓ Stages: 2 (design) Stages: 3 (AI added ✦) AUTO ✓ FIRST-PASS VERIFIED 3-stage · 4h 28m · 0 iterations design cycle complete · 4h 28m · AI added stage 3
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The Challenge

Analog design is one of engineering's
last great bottlenecks.

Analog chip design has remained one of the most time-intensive and expert-dependent stages of semiconductor development. Every new generation of hardware demands more of it — and the industry is feeling the pressure.

The engineers who do this work are rare. The timelines are long. The cost is high. And as semiconductor nodes shrink, the challenge compounds.

"Every time we shrink to a new node, the analog work roughly doubles in complexity. We have the same number of engineers we had five years ago. The math doesn't work anymore."
Senior Director · Leading Design Automation Firm
◷
Long Development Cycles
Bringing an analog chip from specification to tape-out takes significant time — time that compounds across every redesign and revision, delaying products and straining teams.
◈
Scarce Expertise
The engineers who design analog circuits are among the rarest in the industry. Demand for their skills continues to grow faster than supply — and a significant number are approaching retirement.
⬆
High Cost of Iteration
Each revision cycle carries a significant cost in time and resource. The industry has long accepted this as unavoidable. We believe it does not have to be.
Our Mission
"Empowering the analog semiconductor industry with speed, cost efficiency, and engineering excellence."

We are a deep-tech company working at the intersection of artificial intelligence and semiconductor design. Our work is focused on making the analog design process faster, more accessible, and more reliable — for the teams that build the world's most critical chips.

Speed
We are significantly compressing the time it takes to move from design specification to verified output — without sacrificing quality or precision.
Cost Efficiency
Our approach makes it possible to achieve more with less — reducing the cost of analog design in a way that is meaningful for teams of any size.
Human Expertise
We work alongside the world's best analog engineers. Their knowledge and judgment remain at the centre of everything we do.
"Our last tape-out took 18 months. Nine of those months were analog. If we could cut that to eight weeks, we'd ship two products a year instead of one."
CEO · Tier-1 Semiconductor Firm
Get in Touch

Start the
conversation.

We are currently engaging with select semiconductor companies, design partners, and investors. Reach out to start the conversation.

Dresden, Germany Bangalore, India Delaware, USA
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Founder & CEO
Dr. Rajeev Ranjan
Email
Rajeev.Ranjan@vedicanalog.com